1. Field of the Invention
The present invention relates generally to the field of memory management and, more specifically, to class dependent clean and dirty policy.
2. Description of the Related Art
One element of a memory subsystem within certain processing units is a Level 2 Cache memory (referred to herein as “L2 cache”). The L2 cache is a large on-chip memory that serves as an intermediate point between an external memory (e.g., frame buffer memory) and internal clients of the memory subsystem (referred to herein as the “clients”). The L2 cache temporarily stores data being used by the various clients. This data may be retrieved from or written to a dynamic random access memory (DRAM). The clients may re-use data that is stored in the L2 cache while performing certain operations.
During a write operation, where a client transmits data that needs to be committed to a DRAM, the data to be written is first transmitted to the L2 cache and is held there until an opportune time to push the data to the DRAM arises. Data present in the data cache is considered “dirty” until the data is written to the DRAM, after which the memory space in the data cache can be cleaned and made available for other data. During a read operation, a client may request data that was previously written during a write operation. If that data is not currently stored in the L2 cache then that data has to be retrieved from the DRAM. A read operation where the data has to be retrieved from the DRAM is processed in significantly more clock cycles than a read operation where the data is retrieved directly from the L2 cache. Thus, overall system performance may be severely impacted if data has to be retrieved from the DRAM for a significant number of read operations.
As is well known, each block of dirty data in the L2 cache has an associated location within a specific bank page of the DRAM, where the dirty data is written. To optimize memory accesses by mitigating delays resulting from waiting for DRAM bank pages to pre-charge, the number of write operations from the L2 cache to a particular DRAM bank page at any given time should be maximized. However, simply maximizing the number of write operations to the DRAM bank page may not strike the appropriate balance of optimizing write operations to the DRAM and allowing data to remain in the L2 cache long enough to be reused so that data requests to the DRAM can be avoided.
As the foregoing illustrates, what is needed in the art is a more efficient mechanism for determining which data should be transmitted from an intermediate cache, such as an L2 cache, to an external memory.